1. Field of the Invention
This invention relates generally to fabrication of isolation regions for semiconductor devices and more particularly to a method of forming shallow trench isolation (STI) regions having boron regions on the trench sidewalls in NMOS areas.
2. Description of the Prior Art
As the design rules is continue to shrink for high density circuit, the inventors understand that the NMOS devices will face the problem of the reverse narrow width effect in shallow trench isolation process. The reverse narrow width effect problem increases the sub -threshold leakage.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,047,359 (Nagatomo), U.S. Pat. No. 5,013,673 (Fuse), and U.S. Pat. No. 5,401,998 (Chiu). Wolf, "Silicon Processing for the VLSI ERA Volume 3", Lattice Press 1995, pp. 222 to 226, describes narrow gate width effects on Threshold voltage.